Synchronous systems often employ Phase Locked Loops (PLLs) and Delay Locked Loops (DLLs) in order to synchronize an internal clock signal to an external clock signal. PLLs, as the name implies, synchronize an output signal with an external signal. A PLL receives the external signal as an input signal and generates the output signal. The output signal is generated by a combination of elements that include a charge pump and a voltage controlled oscillator. The output signal, however, is not the same signal as the input signal. The output signal is a generated signal that is designed to have the same frequency (or multiple of the frequency) of the input signal.
DLLs, on the other hand, synchronize an output signal, by delaying an input signal. The output signal is a delayed version of the input signal. The input signal is delayed so that the output signal is at a desired phase. For example, an Application Specific Integrated Circuit (ASIC) may use a DLL so that it can synchronize an incoming data stream from a processor with the processor's associated clock signal. Often times, the data stream and the clock signal may not be received by the ASIC at the same time. The received clock, for example, may be a fraction of a period ahead of the received data stream (due to transmission delays). In order to process the data stream correctly, the ASIC may require that the received data stream and the clock be in phase. The ASIC may employ a DLL to delay the received clock signal so that it is delayed to be in phase with the data stream. However, in other ASIC designs, a phase difference, such as 90 degrees, may be desired. Circuits down stream may use such a phase difference to retime received data, for example.
One limitation to conventional DLLs is that they may offer only a limited number of available delay times or phases. For example, phase delay increments of a quarter phase may only be available to a given DLL. In addition, in conventional DLLs, increasing the number of delay increments may increase the overhead associated with the DLL (e.g., size, power consumption, etc.).
Conventional DLLs are also limited because they are not easily programmable. A circuit employing a DLL may have requirements for the phase, or delay of a signal that is application specific. For example, in the ASIC described above, the ASIC may need to be reprogrammed for a different application, the delay requirements of the ASIC may change, or a new DLL may need to be fabricated with a specific delay time.
Therefore, there is a need for an improved DLL.